Dynamic random access memory (DRAM) stores data on small capacitors. Because the charge on the small capacitor leaks away through multiple different leakage paths, the memory has to refresh the cell capacitor periodically and thus not static. DRAM can't be accessed by user operation during self-refresh operation, user operation needs to wait until refresh is finished. Thus the refresh timing impacts the performance of the memory and system. With the development of higher density DRAM and smaller feature size, the refresh operation may take longer time. Conventional solution for reducing refresh penalty is to use comparator to detect user address and refresh address conflict. If user operation and refresh operation are on different banks or on different row addresses, both operations can work at same time. Nevertheless, if addresses of both operations are the same and there is an address conflict, either the refresh operation has to abort or the user read operation has to wait. In such scenarios, the memory user read performance is downgraded and constant user read speed cannot be ensured across address scope.
Therefore, a dynamic random access memory with read address conflict free and refresh transparent to user is desired.